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[Other resource] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45110 | Author: 蔡孟颖 | Hits:

[Other resource] jop_rom

Description: JOP的RAM VHDL源码，经典的经典，不易找到的好东东，-JOP of RAM VHDL source code, classic classics, difficult to find a good price.
Platform: | Size: 4073 | Author: 黄肖超 | Hits:

[Other resource] CapacityRAMModel

Description: Capacity RAM Model的VHDL的例子。最佳的资源优化版。-Capacity Model RAM VHDL example. The best resource optimization version.
Platform: | Size: 3514 | Author: 周阳 | Hits:

[Embeded-SCM Develop] dualportRAM

Description: 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
Platform: | Size: 90116 | Author: 王雪松 | Hits:

[Other resource] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2661 | Author: nick | Hits:

[Other resource] ram

Description: VHDL 编写的RAM例子
Platform: | Size: 2130 | Author: 王攀 | Hits:

[Other resource] ram

Description: fpga中ram的vhdl的经典程序，适用于ALTERA公司器件
Platform: | Size: 1414 | Author: gcy | Hits:

[Other resource] VHDL

Description: 注1： 含有不可综合语句，请自行修改 注2： 一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化
Platform: | Size: 43546 | Author: 朱明 | Hits:

[Other resource] VHDL-ram_fifo

Description: VHDL的ram和fifo model code 包含众多的厂家
Platform: | Size: 1678507 | Author: SL | Hits:

[Picture Viewer] VGA图像显示

Description:

该项目能将RAM或ROM存储器中储存的十六进制数据显示在VGA显示器上，使用VerilogHDL]语言，在Altera的QuartusII下编译通过。


Platform: | Size: 18145 | Author: submars | Hits:

[Documents] 自动售货机VHDL程序与仿真

Description: library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PL_auto1 is port ( clk:in std_logic; --系统时钟 set,get,sel,finish: in std_logic; --设定、买、选择、完成信号 coin0,coin1: in std_logic; --5角硬币、1元硬币 price,quantity :in std_logic_vector(3 downto 0); --价格、数量数据 item0 , act:out std_logic_vector(3 downto 0); --显示、开关信号 y0,y1 :out std_logic_vector(6 downto 0); --钱数、商品数量显示数据 act10,act5 :out std_logic); --1元硬币、5角硬币 end PL_auto1; architecture behav of PL_auto1 is type ram_type is array(3 downto 0)of std_logic_vector(7 downto 0); signal ram :ram_type; --定义RAM signal item: std_logic_vector(1 downto 0); --商品种类 signal coin: std_logic_vector(3 downto 0); --币数计数器 signal pri,qua:std_logic_vector(3 downto 0); --商品单价、数量 signal clk1: std_logic; --控制系统的时钟信号 begin .。。。。。。。。。。。。。
Platform: | Size: 204288 | Author: niuyuanlai@163.com | Hits:

[VHDL-FPGA-Verilog] fifo的vhdl原代码

Description: 本文为verilog的源代码-In this paper, the source code for Verilog
Platform: | Size: 22528 | Author: 艾霞 | Hits:

[VHDL-FPGA-Verilog] 44vhdl

Description: 44个vhdl实例 注1： 含有不可综合语句，请自行修改 注2： 一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化-44 VHDL examples Note 1 : Includes an integrated statement, the initiative to revise Note 2 : Some PLD only allows I/O external three states, do not support the internal three-state, the use of attention to Note 3 : Design RAM is the best way to use devices provide manufacturers with the software automatically generating RAM components, and the VHDL process cases of
Platform: | Size: 44032 | Author: 土木文田 | Hits:

[VHDL-FPGA-Verilog] sdram_vhdl_lattice

Description: sdram_vhdl_lattice，程序已经调通过了，欢迎使用，多多交流哈-sdram_vhdl_lattice, procedures have been transferred through the use of welcome, many exchanges Kazakhstan
Platform: | Size: 181248 | Author: 蒋谦 | Hits:

[VHDL-FPGA-Verilog] SimpleRAMModel

Description: 一个SIMPLE RAM ACCESS的VHDL很经典的例子，我老师的作品。-a SIMPLE RAM ACCESS VHDL classic example of my teacher's work.
Platform: | Size: 3072 | Author: 周阳 | Hits:

[VHDL-FPGA-Verilog] CapacityRAMModel

Description: Capacity RAM Model的VHDL的例子。最佳的资源优化版。-Capacity Model RAM VHDL example. The best resource optimization version.
Platform: | Size: 3072 | Author: 周阳 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_Controller

Description: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Platform: | Size: 677888 | Author: 钟方 | Hits:

[Algorithm] data_convert

Description: 十进制小数转化二进制小数(补码形式输出),对RAM或ROM设置初值极其方便-decimal metric system conversion binary decimal (Complement forms output), the RAM or ROM set initial extremely convenient
Platform: | Size: 1024 | Author: 华少洪 | Hits:

[VHDL-FPGA-Verilog] 用vhdl写实用96例子

Description: 用vhdl写实用96例子, 有RAM，PID 等(Using VHDL to write practical examples of 96, there are RAM, PID and so on)
Platform: | Size: 17153024 | Author: 朱朱8 | Hits:

[Other] 75_RAM

Description: fpga中对RAM的VHDL程序，非常之实用(FPGA in the RAM VHDL procedures, very practical)
Platform: | Size: 1024 | Author: 猪头2005 | Hits:
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